In a conventional lateral MOSFET current flows horizontally from source to drain (both source and drain regions doped with a material of a first conductivity type) along a narrow channel doped with a material of a second conductivity type. A voltage applied to a gate contact overlying the channel inverts the conductivity of the channel, allowing majority carriers to flow from source to drain. Because the channel is narrow, conventional MOSFETS have small drain currents and correspondingly low power ratings.
Power (high current) MOSFETS use many different device geometries to increase the device's maximum current and power rating. These devices have current ratings from about 1 A to 200 A and power ratings from about 1 W to more than 500 W. A typical power MOSFET is not a lateral device. Instead, current flows from a source region on a top surface of the device vertically to a drain region on a bottom surface. This vertical channel configuration allows packing more channels (and more MOSFETS) in a smaller area than a lateral MOSFET. A single die can carry more parallel vertical MOSFET elements than horizontal (lateral) MOSFET elements.
There are three types of so-called vertical MOSFETs: planar double-diffused, trench-gated, and pillar-gated. Each configuration has a unique configuration and fabrication methodology.
In the planar double-diffused type, carriers (electrons in an NMOS device) flow from a first doped region (the source) along a top surface of the device, through the channel in a body region, and then turn downwardly to a second doped region on the bottom surface (the drain). The gate is located on the top surface of the device overlying the channel. The body/channel region is formed of an opposite-conductivity material than the drain and source regions. These planar double-diffused vertical MOSFETs have a higher current capacity than their lateral counterparts.
In the trench-gated MOSFET, the gate is formed in a trench that extends vertically or near-vertically downwardly from the top surface of the device. The channel regions are formed along sidewalls of the trench. The source and drain regions can be located on a top surface of the semiconductor bulk or disposed on opposing surfaces of the bulk. Trench-gated devices are advantageous because they occupy less surface area than vertical double-diffused MOSFETs and consequently enjoy a higher device density. Pillar-gated devices are the converse of the trench-gated device.
Enhancing semiconductor device performance and increasing device density (more devices per unit area) have always been and will always be important objectives of the semiconductor industry. Device density is increased by making individual devices smaller and packing devices more compactly. Packing more devices into the same area, or even better into a smaller area, allows higher levels of system integration and in the case of power MOSFETS, increased current capacity. Since the channel length consumes considerable space in the conventional lateral MOSFET, a vertical channel conserves considerable space.
As device dimensions (also referred to as the feature sizes or design rules, and typically referring to the gate mask dimension) decrease to pack the devices more closely, methods for forming devices and their constituent elements must adapt to the smaller feature sizes. But shrinking device dimensions encounters certain manufacturing limitations, especially with respect to lithographic processes. Fabricators of such devices have therefore sometimes turned to the use of self-alignment techniques to form the various device features.
FIG. 1 illustrates a simple prior art vertical NMOSFET 10 with two source contacts (ohmic contact) 14 on each side of a gate oxide 16. A gate contact 18 overlies the gate oxide 16. N+ source regions 20 are formed in a P− well 24A. An extension of the P− well 24A comprises a P+ region 24B. The source contacts 14 short each of the N+ source regions 20 to the proximate P+ region 24B. Hereinafter, dopants for doping various MOSFET regions may be referred to as dopants of a first or a second conductivity type, where dopants of a first conductivity type can be n-type dopants or p-type dopants, and similarly dopants of the second conductivity type can be n-type dopants or p-type dopants.
An N− epitaxial drift layer 26 is disposed as shown, and an N+ substrate 28 is disposed below the N− epitaxial layer 26. A drain contact 30 is formed on the N+ substrate 28.
When a gate-source voltage is greater than a gate-source threshold voltage, (which is a characteristic of the device) channel regions 24A within the P-wells 24 are inverted. Free electrons then flow from the source regions 20 through the inverted channel regions 24A and vertically downwardly to the drain 30 along paths indicated generally by a reference character 40. Because the conducting channel is much wider than in a conventional lateral MOSFET, the current can be much larger, permitting the vertical MOSFET (VMOSFET) to function at the current and power levels required of a power MOSFET. NMOSFETS are almost universally used in high power MOSFET applications.
To increase the current capacity of a vertical power MOSFET, a geometric pattern of individual MOSFET cells (a cell comprising the vertical MOSFET 10 illustrated in FIG. 1, for example) is formed on a substrate and the MOSFETS connected in parallel. The individual cells may be in the shape of a closed figure, such as a square or hexagon, or they may be arranged in parallel longitudinal stripes. Generally, because of their operational characteristics and geometry, parallel-connected power MOSFETS have equal drain currents. In fact, it is this feature that permits parallel connection of the MOSFETS.
FIGS. 2 and 3 illustrate a top view and a cross-sectional view, respectively, of a prior art geometric pattern of cells arranged in a series of parallel longitudinal stripes. Only two adjacent MOSFETS 38 and 39 are illustrated in FIG. 2. A boundary between the MOSFETS 38 and 39 is defined by adjacent gate contact stripes 40L and 40R, which together define a gate 40. A leftmost boundary of the cell 38 is defined by a gate stripe 44L and a rightmost boundary of the cell 39 is defined by a gate stripe 46R. However, the gate stripe 44L and the gate stripe 44R comprise only one-half of their respective gates, as another gate stripe (not shown) is adjacent each of the gate stripes 44L and 44R.
Continuing with FIG. 2, an interior of the cell 38 comprises source stripes 52L and 54L and an intermediate body stripe 56L. An interior of the cell 39 comprises source stripes 58R and 60R and an intermediate body stripe 62R. The source stripes 52L, 54L, 58R and 60R and the body regions 56L and 62R are connected to respective contacts not illustrated. As shown in FIG. 3, the body region 62R extends below the source regions h58R and 60R and the body region 56L extends below the source regions 52L and 54L.
Channels are formed in the body region 62R at regions 70R and 72R by action of a voltage applied to the respective gate contacts 40R and 46R. Channels are formed in the body region 56L at locations 80L and 82L by applying a voltage to the respective gates 40L and 44L. The body regions and the source regions may be shorted to prevent a parasitic bipolar transistor (as formed at the junction) from turning on.
Continuing with FIG. 3, gate oxide layers 90L, 92L, 94R and 96R underlie the respective gate contacts 44L, 40L, 40R and 46R. An N-epitaxial layer 90 and a substrate 94 underlie the various doped regions as illustrated. A drain contact 99 is disposed on a back or bottom surface as shown.
A voltage applied to the gate contacts 44L, 40L, 40R and 46R inverts the channel regions 82L, 80L, 70R and 72R, permitting carriers to flow from the source regions 54L, 52L, 58R and 60R through the inverted channel regions to the drain contact 99.
The channel resistance is one of the largest components of the total on-state resistance between the source and drain in a MOSFET, referred to as RDS(ON). The other resistive components arise in a vertical or power MOSFET due to: source contact resistance, resistance to lateral flow of electrons across the source, channel resistance, JFET resistance through a constricted channel along the surface current path between the P-well regions, resistance across the N− epitaxial region (the current spreads out as it flows vertically), substrate resistance as the current flow vertically across the N+ substrate, and finally drain contact resistance. The channel resistance component can be as much as about 40% of RDS(ON) for a 1200 volt SiC device, which is in part due to the poor mobility of the inversion layers in SiC. Thus short channels and high channel density may be desired.
The channel resistance is directly related to the mobility of the carriers within the (inverted) channel. For a silicon MOSFET the carrier mobility is about 200 cm2/V-s. For silicon carbide the mobility falls to about 20 cm2N-s. Thus silicon carbide material has a higher channel resistance. To overcome this disadvantage of silicon carbide, it is desirable to make the channel very short and densely pack them to increase the number of vertical channels per unit area. The vertical channels within the device are connected in parallel and act like parallel resistors, which therefore lowers the total channel resistance of the power MOSFET. The more channels that can be squeezed into a unit area the smaller the resistance of the parallel-connected MOSFET channels.
Notwithstanding its greater channel resistance, silicon carbide offers certain advantages over a silicon power MOSFET. These advantages are a consequence of the inherent material characteristics of SiC over Si, including a wider bandgap (3.2 eV), a higher voltage breakdown strength (2.2 MV/cm) and a higher thermal conductivity (˜3W/cm-K). But processing issues associated with the use of SiC material, including poor SiC-oxide interfaces and premature breakdown of the gate oxide, have disfavored widespread use of this material for commercial devices.
Various fabrication processes and device structures have been used to provide accurate and reliable regions of power MOSFET devices, some of which have been described above. However, continued improvements are needed, especially as feature dimensions shrink and alignment tolerances become more difficult to satisfy. But self alignment techniques provide accurate and repeatable device structures and therefore increases device yield. Therefore use of self alignment techniques while shrinking feature sizes allows the devices to be packed more tightly. Shrinking cell dimensions reduces the channel length, lowering the ON state channel resistance (RDS(ON)).